Notice Board :

Call for Paper
Vol. 7 Issue 1

Submission Start Date:
January 1, 2021

Acceptence Notification Start:
January 20, 2021

Submission End:
January 25, 2021

Final ManuScript Due:
January 29, 2021

Publication Date:
January 31, 2021
                         Notice Board: Call for PaperVol. 7 Issue 1      Submission Start Date: January 1, 2021      Acceptence Notification Start: January 20, 2021      Submission End: January 25, 2021      Final ManuScript Due: January 29, 2021      Publication Date: January 31, 2021



Volume IV Issue II

Author Name
Ashutosh Kumar Yadav, Prof.Ashish Raghuwanshi
Year Of Publication
2018
Volume and Issue
Volume 4 Issue 2
Abstract
Full Adder is the heart of any central processing unit that is a core component employed in all the processors. This thesis presents a design methodology using pass transistor logic and transmission gates for the architecture of full adder with minimum number of transistor i.e.
PaperID
IJETAS/February/2018/03

Author Name
Priyanka Bharadwaj, Prof.Ashish Raghuwanshi
Year Of Publication
2018
Volume and Issue
Volume 4 Issue 2
Abstract
In this paper, Authors have presented the literature on coming up with of high speed, less area 64-bit ALU using economical techniques. The optimization of the projected style can be done by using the various techniques. The parameters speed and area of the projected style can be improved by using Carry Look Ahead Techniques.
PaperID
IJETAS/February/2018/05