Notice Board :

Call for Paper
Vol. 7 Issue 10

Submission Start Date:
October 1, 2021

Acceptence Notification Start:
October 20, 2021

Submission End:
October 25, 2021

Final ManuScript Due:
October 28, 2021

Publication Date:
October 31, 2021
                         Notice Board: Call for PaperVol. 7 Issue 10      Submission Start Date: October 1, 2021      Acceptence Notification Start: October 20, 2021      Submission End: October 25, 2021      Final ManuScript Due: October 28, 2021      Publication Date: October 31, 2021



Volume IV Issue III

Author Name
Priyanka Bharadwaj, Prof.Ashish Raghuwanshi
Year Of Publication
2018
Volume and Issue
Volume 4 Issue 3
Abstract
Full Adder, which is the core of any arithmetic and logic unit that is the main component used in all the processors. This correspondence presents a design technique using pass transistor logic (PTL) and transmission gates for the architecture of full adder with minimum number of transistor and reduced delay.
PaperID
IJETAS/March/2018/08

Author Name
Pooja Jain, Prof.Dilip Ahirwar, Prof.Anupreksha Jain
Year Of Publication
2018
Volume and Issue
Volume 4 Issue 3
Abstract
The Booth multiplier has been widely used for high performance signed multiplication by encoding and thereby reducing thenumber of partial products. A multiplier using the radix-4 (or modified Booth)
PaperID
IJETAS/March/2018/13

Author Name
Swati Nema, Prof.Geetesh Wagadre, Prof. Jitendra Mishra
Year Of Publication
2018
Volume and Issue
Volume 4 Issue 3
Abstract
To identify the present or absent of licensed users, spectrum sensing techniques are used. Matched filter detection, Energy detection, and Cyclo-stationary feature detection are the three conventional methods used for spectrum sensing.
PaperID
IJETAS/March/2018/17

Author Name
Bhagyalaxmi Patsariya, Prof.Susmita Bilani, Prof.Dilip Ahirwar, Prof.R. S. Pandey
Year Of Publication
2018
Volume and Issue
Volume 4 Issue 3
Abstract
In this paperthearchitecture designsspeed andarea efficienttransistor base adder usingstaticCMOSpasstransistorlogic.Inthisworkthe longest critical path shortened to decreasethetotal criticalpath delay.
PaperID
IJETAS/March/2018/21